 ---------------------------------------------------------------------------------
  -- Design Name : Control lines
  -- File Name   : WbCtrl.vhd
  -- Function    : Create control lines based on opcode
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.UserPkg.all;

entity WbCtrl is
  port (
    op:           in  opCode;
    wbSel:        out std_logic_vector(1 downto 0);
    wr:           out std_logic;
    rwr16:        out std_logic;    
    loRts:        out std_logic
  );
end WbCtrl;

architecture behavioral of WbCtrl is
begin 
/*
  wbSel <= "10" when op = OPC_POP  or op = OPC_RTS else           
           "01" when op = OPC_LOAD                 else
           "00";
           
  wr    <= '1' when op = OPC_LOAD or
                    op = OPC_MOVI or
                    op = OPC_POP  or
                    op = OPC_ADD  or
                    op = OPC_ADDI or
                    op = OPC_SUB  or
                    op = OPC_SUBI or
                    op = OPC_AND  or
                    op = OPC_OR   or
                    op = OPC_XOR  or
                    op = OPC_NOT  or
                    op = OPC_SHL  or
                    op = OPC_SHR  or
                    op = OPC_SAR  or
                    op = OPC_ROL  or
                    op = OPC_ROR  or
                    op = OPC_MOV  else
            '0';
                    
   rwr16 <= '1' when op = OPC_MOVI else
            '0';
            
   loRts <= '1' when op = OPC_RTS else
            '0';        
*/

 process(op)
 begin
    wbSel       <= "00";
    wr          <= '0';
    rwr16       <= '0';
    loRts       <= '0';    
           
    case op is
      when OPC_LOAD =>
        wbSel       <= "01";
        wr          <= '1';
      
      when OPC_MOVI =>
        wbSel       <= "00";
        wr          <= '1';
        rwr16       <= '1';
        
      when OPC_POP =>
        wbSel       <= "10";
        wr          <= '1';
      
      when OPC_RTS =>
        wbSel       <= "10";
        loRts       <= '1';
        
      when OPC_ADD | OPC_ADDI | OPC_SUB | OPC_SUBI | OPC_AND | OPC_OR | OPC_XOR | OPC_NOT | 
           OPC_SHL | OPC_SHR | OPC_SAR | OPC_ROL | OPC_ROR | OPC_MOV                        =>
        wbSel       <= "00";
        wr          <= '1';
        
      when others =>
        wbSel       <= "00";
        wr          <= '0';
        rwr16       <= '0';
        loRts       <= '0';
                
     end case;
  end process;
  
end architecture;